Complexity in processor micro architecture and the related issues of power density, hot spots and wire delay, are seen to be a major\nconcern for design migration into low nano meter technologies of the future. This paper evaluates the hardware cost of an alternative\nto register-file organization, the super scalar stack issue array (SSIA).We believe this is the first such reported study using discrete\nstack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding\ndelay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a\n4-wide issue rate of at least four Giga-ops/sec at 90nm and opportunities for twofold future improvement by using more advanced\ndesign approaches.
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